1. Field of the Invention
The present invention generally relates to a semiconductor electronic device structure comprising dielectric layers having improved adhesion to other dielectric or conducting layers. More particularly, the present invention relates to using a layer of amorphous silicon (a-Si) or amorphous Germanium (a-Ge) (or alloys thereof) as an adhesion enhancing interfacial layer. Furthermore, the present invention relates to a method for improving the adhesion between different dielectric or conductive layers including those that include Si or C.
2. Description of the Prior Art
The continuous shrinking in dimensions of electronic devices utilized in ULSI circuits in recent years has resulted in increasing the resistance of the BEOL metallization as well as increasing the capacitance of the intralayer and interlayer dielectric. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) insulators and particularly those with k significantly lower than silicon oxide are being introduced to reduce the capacitances.
The low-k materials that have been considered for applications in ULSI devices include polymers containing Si, C, O and H, such as methylsiloxane, methylsilsesquioxanes, and other organic and inorganic polymers which are fabricated by spin-on techniques or, Si, C, O and H containing materials (SiCOH, SiOCH, carbon-doped oxides (CDO), silicon-oxicarbides, organosilicate glasses (OSG)) deposited by plasma enhanced chemical vapor deposition (CVD) techniques. The incorporation of the low-k dielectrics in the interconnect structures of integrated circuits (IC) often requires the use of other dielectric materials as diffusion barrier caps or etch-stop and chemo-mechanical polishing (CMP) hardmasks. The adhesion between the different layers in the complex structures of an IC device is often too low, resulting in delaminations during the processing of the device. This is especially true for adhesion of dielectric or metallic layers to SiO2. Furthermore, an intermediate layer of refractory metal nitride is generally needed to provide suitable adhesion between the metallic Cu-diffusion barrier and the dielectric insulator of the interconnect structure. The conductive nitride layer, typically of lower conductivity than the metallization layers occupies a significant thickness of the shrinking metallization and increases its resistivity. The elimination of this conductive nitride layer by substituting it with a very thin adhesion layer can improve the performance of ULSI devices.
It would thus be highly desirable to provide a semiconductor device comprising an insulating structure including comprising a multitude of dielectric and conductive layers with good adhesion between the different layers, and a method for manufacturing said semiconductor device.
As described in U.S. Pat. No. 4,647,494, amorphous Silicon (a-Si) of tens of Angstroms thick has been recognized for improving adhesion of wear resistant carbon coatings to metallic magnetic recording layers in recording tapes and disks. That is, in U.S. Pat. No. 4,647,494, a-Si is described as improving adhesion between amorphous hydrogenated carbon (or diamondlike carbon) and silicide forming metals. The use of thin a-Si bonding layer has not been utilized in semiconductor ULSI manufacturing processes to enhance adhesion between dielectric layers of a semiconductor BEOL wiring structure.
It would thus be further highly desirable to provide a semiconductor device structure and method for manufacturing an insulating structure comprising a multitude of dielectric and conductive layers that includes thin a-Si, a-Ge or alloys thereof, bonding layers used to enhance adhesion between the different layers.
It is therefore an object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers with good adhesion between the different layers.
It is a further object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin bonding layer comprising amorphous Si (a-Si), amorphous Ge (a-Ge) or alloys thereof, wherein the thin a-Si (a-Ge or alloys thereof) may be hydrogenated or non-hydrogenated.
It is another object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin amorphous bonding layer comprising amorphous Si (a-Si), amorphous Ge (a-Ge) or alloys thereof, wherein the thin a-Si (a-Ge or alloys thereof) may be at least partially oxidized.
It is another object of the present invention to provide an insulating structure including a thin intermediate a-Si (a-Ge or alloys thereof) bonding layer adhesion layer for enhancing adhesion between an oxide layer, e.g., from the group comprising SiO2, phosphorus silicate glass (xe2x80x9cPSGxe2x80x9d) or boron phosphorus silicate glass (xe2x80x9cBPSGxe2x80x9d), and a layer from the group comprising SiCOH, SiC, SiCN, SiCH, or SiCNH.
It is yet another object of the present invention to provide an electronic device structure incorporating layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure in which the adhesion between different dielectrics is enhanced by a thin intermediate a-Si bonding layer, or a bonding layer of a-Ge or alloys thereof.
It is still another object of the present invention to provide an electronic device structure incorporating layers of insulating and conductive materials as intralevel or interlevel dielectrics in a BEOL wiring structure in which the adhesion between the conductive layers and the different dielectric layers is enhanced by a thin intermediate a-Si bonding layer, or a bonding layer of a-Ge or alloys thereof.
It is still yet a further object of the present invention to provide a method for fabricating an a-Si adhesion layer (or a layer of a-Ge or alloys thereof) either in a parallel plate plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) reactor or, in a sputtering reactor.
It is yet another object of the present invention to provide an electronic device structure, which comprises at least one a-Si bonding layer (or a layer of a-Ge or alloys thereof) between a dielectric layer and a liner/barrier layer for a Cu metallization structure.
It is another object of the present invention to provide an insulating semiconductor structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin amorphous Si (a-Si) bonding layer (or a layer of a-Ge or alloys thereof) which may be at least partially oxidized.
According to the principles of the invention, there is provided a method for fabricating a BEOL interconnect structure with improved adhesion between the layers of the structure. The present invention further provides an electronic device structure that incorporates a-Si layers (or layers of a-Ge or alloys thereof) between dissimilar layers in the structure to improve the adhesion between them. In one embodiment, a thin a-Si layer, 1-100 nm, preferably 2-6 nm thick, is interposed between a silicon oxide layer and a SiCOH layer, enhancing the adhesion between the two layers. In another preferred embodiment, the 1-100 nm, preferably 2-6 nm thick a-Si layer is interposed between a SiCOH dielectric layer and a layer of SiN, SiC, SiCH, or SiCHN, to enhance the adhesion between the layers. In yet another embodiment, the 1-100 nm, preferably 2-6 nm thick a-Si layer is interposed between a dielectric layer and a Ta layer, to enhance the adhesion between the two layers.
In yet another embodiment, the a-Si layer (or a layer of a-Ge or alloys thereof) is incorporated between any two layers from the group comprising SiO2, PSG, BPSG, SiN, SiC, SiCH, SiCHN, or SiCOH, Ta, Ti, and any other silicide forming metal, to improve the adhesion between the layers.
In an embodiment, the a-Si layer (or a layer of a-Ge or alloys thereof) is deposited after the hardmask layer which may be comprised of SiO2, PSG, BPSG, SiN, SiC, SiCH or SiCHN which is then followed by the liner material such as Ta, Ti, W or their nitrides or silicides. The a-Si layer allows for the pure form of the metal to be deposited without concern for delamination on the metal/hardmask interface during CMP. The further benefit of depositing the pure metal is found at the via/line interface where pure metallic bonding is created which guarantees good adhesion and improves device reliability especially for thermal excursions and also has the added benefit of reducing contact resistance.
In another aspect of the invention, there is provided a method for fabricating a multilayered structure with strong adhesion between the different layers comprising the steps of: providing a plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) reactor: positioning an electronic device structure (i.e., substrate) having an upper layer of first dielectric in the reactor; flowing SiH4 or SiH4 diluted in an inert gas into the reactor; depositing a layer of a-Si on top of said substrate; flowing precursors into the reactor for depositing a second dielectric or conductive layer on top of the a-Si bonding layer. The second dielectric layer is preferably a SiCOH type dielectric of low dielectric constant (k less than 3.2) or ultralow dielectric constant (k less than 2.4) or a metal such as Ta, Ti, W, combinations of the previous, their silicides and/or nitrides.
In another embodiment, the step of depositing the a-Si adhesion layer (or a layer of a-Ge or alloys thereof) is repeated after the deposition of said second layer.
In yet another embodiment the a-Si layer (or a layer of a-Ge or alloys thereof) is at least partially oxidized by exposing it to an oxygen plasma after its deposition.
In a different embodiment, the substrate is removed from the PECVD reactor after the deposition of the a-Si layer and a said second dielectric layer from the group comprising organic polymers, silicon based polymers, organic glasses, hybrid Si and C containing polymers, oxides, or porous modifications of same materials is deposited by a spin-on method.
In yet a different embodiment, the substrate is removed from the PECVD reactor after the deposition of the a-Si layer and after exposing the a-Si layer to an oxygen plasma and a second dielectric layer from the group comprising organic polymers, silicon based polymers, organic glasses, hybrid Si and C containing polymers, oxides, is deposited by a spin-on method.
Dielectric layers such as ones aforementioned, or layers of metals that form silicides have good adhesion to the a-Si interlayer, therefore the a-Si intermediate layer enhances the adhesion between such layers. The a-Si can be deposited by any radiation assisted techniques, such as PECVD, high density plasma, sputtering, ion beam sputtering, ion beam deposition.
The adhesion enhancing a-Si layer can be used in the back end of the line (BEOL) structure of a CMOS device to improve the adhesion between a low-k dielectric, e.g. SiCOH, and SiO2 or between a metal layer, e.g. Ta, and a dielectric.
The present invention is further directed to an electronic device structure which has layers of insulating materials as intralevel or interlevel dielectrics in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) interconnect structure which includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, an adhesion layer of a-Si (or a layer of a-Ge or alloys thereof) between the second layer of insulating material and first layer of insulating material, the first region of conductor being in electrical contact with the first region of metal, and a second region of conductor being in electrical contact with the first region of conductor and being embedded in a third layer of insulating material, the third layer of insulating material contacting with the second layer of insulating material. The electronic device structure may further comprise a dielectric cap layer situated in between the second layer of insulating material and the third layer of insulating material and including a-Si adhesion layers between the cap layer and the second and optionally the third insulating layers.
The electronic device structure may further comprise a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material and containing a-Si adhesion layers between the cap layers and the insulating layers.
The dielectric cap material can be selected from silicon oxide, silicon nitride, silicon oxynitride, a refractory metal silicon nitride (wherein the refractory metal is selected from the group consisting of Ta, Zr, Hf and W) silicon carbide, carbon doped oxide or SiCOH and their hydrogenated compounds. The first and the second dielectric cap layers may be selected from the same group of dielectric materials. The first layer of insulating material may be silicon oxide or silicon nitride or doped varieties of these materials, such as phosphorus silicate glass (xe2x80x9cPSGxe2x80x9d) or boron phosphorus silicate glass (xe2x80x9cBPSGxe2x80x9d), SiC, SiCN, SiCH, or SiCNH. The second and subsequent dielectric layers may be PECVD deposited SiCOH or spin-on deposited dielectrics.
The electronic device structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layers of insulating material with an a-Si intermediate adhesion layer (or an adhesion layer of a-Ge or alloys thereof). The electronic device structure may further comprise a dielectric on top of the second layer of insulating material, which acts as a reactive ion etch (xe2x80x9cRIExe2x80x9d) hard mask and polish stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask and polish stop layer, with an a-Si intermediate adhesion layer between said top dielectric and said second layer of insulating material. The electronic device structure may further comprise a first dielectric RIE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RIE hard mask/diffusion barrier layer on top of the first dielectric polish-stop layer, a second dielectric RIE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer with a-Si adhesion layers between two layers of different materials. The electronic device structure may further comprise a dielectric cap layer of same materials as mentioned above, between an interlevel dielectric and an intralevel dielectric.
Advantageously, the method for improving the adhesion between the different layers of an electronic device structure using the a-Si adhesion layer is implemented in a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring process. Thus, the electronic device structure comprises at least one a-Si bonding layer between the dielectric and conductive layers of a back-end-of-the-line (xe2x80x9cBEOLxe2x80x9d) wiring structure.